This invention generally relates to digital data processing systems. More specifically it relates to a central processor for use in such data processing systems.
A digital data processing system comprises three basic elements: namely, a memory element, an input-output element and a processor element. The memory element stores information in addressable storage locations. This information includes data and instructions for processing the data. The processor element transfers information from the memory element. It interprets the incoming information as either data or instructions. An instruction includes an operation code that specifies, in coded form, the operation to be performed by the processor. An instruction may also include information that specifies one or more addresses for operands. This information is called an operand specifier.
Different data processing systems utilize a wide variety of methods for specifing an operand address. The foregoing U.S. Pat. No. 3,614,741 describes an operand specifier containing a register address and mode descriptor. The mode descriptor enables the programmer to define the location of the operand, which can be in the next program location in the memory element, in a register designated by the register address, or in a location which is specified by an address that is calculated with the information stored in the designated register. It also is possible in this specific data processing system to provide an indexed mode of addressing. This is accomplished by specifying the program counter as the designated register. The system then utilizes the contents of the program counter as a base address and the word following the instruction is interpreted as an index value which is added to the base address to obtain either the operand address or the address of the operand address.
Other data processing systems use other types of addressing. For example, in one such system an instruction is formatted to contain a field devoted to indexed addressing. This field specifies an index register and uses a predetermined default value to inhibit indexed addressing. However, these instructions are used many times so the amount of memory that is required, but not needed for instructions which do not invoke indexed addressing, can become quite large. In other systems a specific register field may be interpreted as designating an index register if it contains a predetermined value or values. For other values the contents of that register field are interpreted in some other way.
All schemes for indexed addressing, known to us, are characterized by two problems. First, the index mode is normally invoked only at the exclusion of other addressing modes or only at the cost of increasing the instruction size to accomodate the indexing control as previously described. Moreover, if indexed addressing is used to obtain consecutive data items, the use of indexing can become complex if the data items themselves are of varying size. Some procedure must be provided for scaling the number in the index register to compensate for these different sizes. In these prior data processing systems this function is left to the programmer to implement or limited to simple cases. If the programmer must perform the function, the programmer's task is further complicated and the size of the overall program increases.
Therefore, it is an object of this invention to provide a data processing system which operates with an improved indexing mode for specifying the address of an operand.
Another object of this invention is to provide a data processing system in which the length of an instruction can be changed to accomodate an indexing operation so that the instruction incorporates indexing information only when needed.
Yet another object of this invention is to provide a data processing system in which the index value is obtained and automatically scaled to the data size.
Still another object of this invention is to provide a data processing system in which indexing can be combined with any other mode of addressing.